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This presentation will work through the latest WaveExt signal integrity tool, its current workflow for analyzing high-speed PCB layouts. This tool is still under development, so any feedback would be greatly appreciated.

Hva har du brukt AI til i det siste? Vi vil at DU skal reise deg opp og si tre setninger om hva du nylig har brukt AI til. Hva var problemet? Hvordan ble det løst? Har du en utfordring som AI ikke kunne hjelpe til med, men som SI-Forum kanskje fikser?

En typisk IO på en moderne FPGA eller mikroprosessor har konfigurerbar driverstyrke, slew-rate, terminering og mer. IO-konfigurasjon påvirker signalintegritet på et kretskort, cross-talk signaler imellom, samt EMC, men blir ofte latt være med default-verdier. Presentasjonen gir en oversikt over hvilke slike brytere designere har tilgjenglig, og deres effekter på og utenfor kretskortet.

As data rates in serial links climb towards 10 GT/s and beyond, the margin for error in the physical layer vanishes. At these frequencies, interconnects can no longer be treated as simple wires, and minor impedance discontinuities can have catastrophic effects on signal integrity. Among the primary adversaries of a clean signal is the phenomenon of reflection - energy bouncing back from impedance mismatches caused by vias, connectors, and package transitions. This presentation provides some theory of the mechanics and mitigation of signal reflections in high-speed digital design. Following the theory, it will examine a simulation workflow. Finally, it will bridge the gap between simulation models and physical reality by presenting real-world measurements from a prototype unit using a Vector Network Analyzer. It will correlate the simulated expectations with the measured reality.